1. Technical Field of the Invention
The present invention relates to a process for fabricating an integrated electronic component and, in particular, to the process for fabricating such a component comprising a limited volume of a specified material, the dimensions of which have to be precisely defined and reproduced identically during mass production.
2. Description of Related Art
Increasing the level of integration of electronic circuits leads to a reduction in the geometrical dimensions of the components that make up these circuits. To take an example, the technology for fabricating field-effect transistors or MOS (Metal Oxide Semiconductor) transistors is designated by the width of the gate of these transistors, this being measured along the direction of flow of the electrical current between the source and the drain of the transistors. Thus, 0.13 and 0.10 micron technologies for fabricating semiconductor components correspond to transistors whose gates have respective widths of 130 and 100 nanometers.
To fabricate components having such levels of integration reproducibly, it is necessary for the processes used to allow for very precise control over the geometrical dimensions of those parts of the components that determine the electrical characteristics finally obtained. This is in particular the case for the gates of MOS transistors.
One method of forming a material of a specified external shape on a substrate consists of depositing, in a first step, a substantially uniform layer of this material on the substrate and then, in a second step, removing this material by etching beyond a part of the substrate defined by a mask. The etching process must be chosen so that said material in its definitive form has sidewalls conforming to the desired geometry, these possibly being, for example, planar sidewalls perpendicular to the surface of the substrate.
However, when said material is in particular a metal, such sidewalls formed by etching a layer deposited beforehand are imperfect on the scale of the levels of integration currently desired. In particular, they are inclined with respect to a direction perpendicular to the surface of the substrate, or even exhibit undulations in this direction.
Moreover, the etching process used must be selective between the material deposited on the substrate and the material of the substrate itself, so as to remove the material deposited beyond the final desired feature, without removing material from the substrate. Without such selectivity, the surface of the substrate is modified during etching, preventing precise control of the height, relative to the surface of the substrate, of the deposited material remaining after the etching step. This selectivity represents a constraint on the choice of materials for the component, which may be incompatible with some of the desired characteristics of said component.
The Damascene process known to those skilled in the art, or its variant “dual Damascene”, constitutes a second method of forming a feature of specified shape on a substrate. This process consists of depositing a layer of an external material on the substrate, in which layer a cavity is formed that will serve as a mold for the material on which a specified shape has to be conferred. The cavity is filled with this latter material, forming an excess above the cavity, so as to guarantee that the cavity is completely filled. The excess fill material is then removed by polishing.
A drawback with the Damascene and dual-Damascene processes stems from the final polishing. This is because the polishing rate depends on the material removed, that is to say the external material or fill material, so that regions having a high feature density are eroded during polishing at a rate different from that of regions having a lower feature density. This results in a loss of planarity of the polishing surface, creating disparities within a series of components fabricated using the processes of this type. Such a loss of planarity after polishing may correspond to variations in the thickness of the layer of external material of up to 150 nanometers, incompatible with 0.10 to 0.13 micron technologies that require this thickness to be controlled to within about 10 nanometers. This planarity requirement will become even more demanding in the case of future integrated circuit fabrication technologies.
For some geometrical configurations, these thickness variations may also cause, during polishing, insufficient removal of the excess fill material. When the fill material is conducting, residual parts of this excess may subsequently cause an electrical short circuit during use of the electrical device incorporating such a component.
There is accordingly a need to produce features of defined materials on a substrate allowing precise control of the geometrical dimensions of said features.